The present invention is related generally to the field of semiconductor memory devices, and more particularly, to an interface circuit and method for a pseudo-static memory device.
A class of memory devices called pseudo-static memory are typically memory devices that are functionally equivalent to static random access memory (SRAM) devices, but include internal refresh circuitry, so that the devices appear to the use as not needing refresh operations. In general, these memory devices can be operated in the same manner one would operate a conventional SRAM, but have a memory core based on conventional dynamic random access memory (DRAM) cells. As is well known in the art, a major distinction between the two types of memory cells is that DRAM memory cells need to be periodically refreshed to maintain the stored data whereas SRAM memory cells do not.
There are advantages to employing a conventional DRAM memory core over a conventional SRAM memory core in a memory device. For example, memory density for a DRAM memory array can be much greater than that for a SRAM memory array. In the case of a DRAM memory cell, only one transfer gate and a storage device, typically a capacitor, is necessary to store one bit of data. Consequently, each DRAM memory cell is considerably smaller than a conventional SRAM memory cell, which may have as many as six transistors per memory cell. The simple structure and smaller size of the DRAM memory cell translates into a less complicated manufacturing process, and consequently, lower fabrication costs when compared to the SRAM memory cell.
In spite of the aforementioned advantages provided by a DRAM memory core, there are issues related to the design and operation of a conventional DRAM memory array that make its application undesirable. For example, as previously mentioned, DRAM memory cells need to be refreshed periodically or the data stored by the capacitors will be lost. As a result, additional circuitry must be included in the memory device to support the refresh operation. It is also generally the case that access times for DRAM memory cores are greater than the access times for SRAM memory cores.
Additionally, a memory access operation for a conventional DRAM memory core is such that once the operation has begun, the entire access cycle should be completed or the data will be lost. That is, a DRAM access cycle begins with a row of memory cells in the array being activated, and the respective charge state of the memory cells for the activated row are sensed and amplified. A column including a particular memory cell of the activated row is selected by coupling the column to an input/output line. At this time, data can be read from or written to the particular memory cell. Following the read or write operation, the row of memory cells is deactivated, thus, storing the charge state in the respective capacitors of the memory cells. As is generally known, the process of sensing the charge state of the memory cells is destructive, and unless the access cycle is completed with the charge state being amplified and the row being deactivated, the data stored by the memory cells of the activated row will be lost. In contrast, for a conventional asynchronous SRAM memory device, the SRAM sense operation is non-destructive and does not have the same type of access cycle as a conventional DRAM memory device. Consequently, random memory addresses may be asserted to the SRAM memory device without timing restriction, and data is always expected to be returned in a certain time thereafter. This time is typically referred to as the address access time tAA.
Therefore, it is desirable to have a circuit that can accommodate the asynchronous nature of an SRAM memory device and transform these actions to the scheduled events of a conventional DRAM memory access operation in order to provide an asynchronous pseudo-static memory device that employs a conventional DRAM memory core.
The present invention is directed to an apparatus and method for converting unrestricted randomly scheduled address transitions of memory address signals into scheduled address events from which initiation of a sequence of memory access events can be based. An address interface circuit includes an address detection circuit that receives a memory address and generates a detection pulse in response to each receipt of a new memory address. Further included in the address interface circuit is a pulse circuit coupled to the address detection circuit. The pulse circuit generates an initiation pulse that initiates a memory access operation after a time delay elapses from receiving the detection pulse from the address detection circuit. However, where another detection pulse is received by the pulse circuit prior to the time delay elapsing, the time delay is reset by the new detection pulse, and the pulse circuit will then generate the initiation pulse following the time delay elapsing from receipt of the new detection pulse. The initiation pulse generated by the pulse circuit can then be used to start a sequence of access events to access a memory array.